thebears
bbdcc1e623
- main.c: file-header comment describing the hardware and operation, logic split into named phases (sleep_until_interrupt, wake_peripheral_rails, take_counts_snapshot, send_wheel_counts_report, handle_minute_alarm, init_all_hardware); shared state renamed to say what it is and made static. - rfm69.c: reorganized into six labeled sections; cond_1/2/3 and hash scratch globals replaced by a reply_acknowledges() helper with clear locals; packet layout and every init register write documented. - LOG() macro (compiled out when DO_UART is off) replaces the #if DO_UART blocks that obscured the logic. - Drivers: file-header comments; named RTC_REG_*/RTC_ALM_MASK_BIT constants; EEPROM spool scheme documented; ADC_CHANNEL_BANDGAP named; repeated pin if/else helpers collapsed to SET_PIN_TO(). - Removed unused globals/buffers and commented-out code; ran clang-format with the project style. Register writes and radio protocol are byte-identical. Builds clean under -Wall -Wextra on gnu17 and c23; flash 13028 -> 12830 B, static RAM 1038 -> 999 B. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01YVJKatfeMJjAmuH9KYiLuv
78 lines
2.0 KiB
C
78 lines
2.0 KiB
C
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#include "interrupts.h"
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void init_pins(void)
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{
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// The reed switch (PD3/INT1) switches to ground and the RTC alarm output
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// (PD2/INT0) is open-drain, so both need the internal pull-up. Leaving them
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// floating makes the inputs self-trigger.
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SET_PIN_IN(DDRD, DDD3);
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SET_PIN_HIGH(PORTD, PD3);
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SET_PIN_IN(DDRD, DDD2);
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SET_PIN_HIGH(PORTD, PD2);
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}
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// Both external interrupts are configured low-level triggered (ISCn1:0 = 00).
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// Edge detection needs the I/O clock, which SLEEP_MODE_PWR_DOWN stops, so a
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// falling-edge INT0/INT1 can never wake the MCU. Only level detection is
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// asynchronous. Each handler masks its own interrupt while the source is still
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// asserted, so the low level does not retrigger in a loop.
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void set_up_reed_interrupt(void)
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{
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EICRA &= ~((1 << ISC11) | (1 << ISC10));
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EIMSK |= (1 << INT1);
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}
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void set_up_minute_interrupt(void)
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{
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EICRA &= ~((1 << ISC01) | (1 << ISC00));
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EIMSK |= (1 << INT0);
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}
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void reed_interrupt_enable(void)
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{
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EIFR = (1 << INTF1); // Drop anything latched while we were masked
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EIMSK |= (1 << INT1);
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}
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void minute_interrupt_enable(void)
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{
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EIFR = (1 << INTF0);
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EIMSK |= (1 << INT0);
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}
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void wdt_isr_enable(void)
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{
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uint8_t sreg = SREG;
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cli();
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wdt_reset();
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// WDRF keeps WDE set, which would block the write below, so it must go
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// first. The unlock is a single assignment: a read-modify-write does not
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// open the 4-cycle change window.
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MCUSR &= ~(1 << WDRF);
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WDTCSR = (1 << WDCE) | (1 << WDE);
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// WDP[3:0] = 0b011 -> 0.125 s. Interrupt mode only (WDE clear), so an
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// expiry wakes us to clear the debounce instead of resetting the part.
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WDTCSR = (1 << WDIE) | (1 << WDP1) | (1 << WDP0);
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SREG = sreg; // Restore, never blanket-sei(): these run inside an ISR
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}
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void wdt_isr_disable(void)
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{
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uint8_t sreg = SREG;
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cli();
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wdt_reset();
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MCUSR &= ~(1 << WDRF);
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WDTCSR = (1 << WDCE) | (1 << WDE);
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WDTCSR = 0x00;
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SREG = sreg;
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}
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