thebears/wheel_rfm69_counter
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Fix wake-from-sleep, RAM overrun, and peripheral hangs in AVR firmware

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Three defects prevented the board from working at all:

- INT0/INT1 were falling-edge triggered. Edge detection needs the I/O
  clock, which SLEEP_MODE_PWR_DOWN stops, so neither the reed switch nor
  the RTC alarm could wake the MCU. Both are now low-level triggered (the
  only asynchronous mode), and each handler masks its own interrupt while
  the source is still asserted so the low level cannot retrigger. The reed
  and RTC pins also get their pull-ups; they were explicitly driven low.

- Statics were 1440 B of 2048 with a 538 B main frame, so the first NFC
  read ran the stack into .data. Shrank the oversized buffers and made the
  NFC scratch buffer static: statics 1440 -> 1038 B, main frame -> 204 B.

- The FIFO was filled after entering TX mode with TxStart = FifoNotEmpty,
  so transmission began before the payload was loaded. Load in standby.

Memory safety: clamp the unvalidated RX length (len - 4 underflowed to
>=252 into a 60-byte buffer), fix writes one byte past DATA_BUFFER_65,
fix the diameter copy length in st25dv.c, NUL-terminate remove_spaces,
and bounds-check the NDEF parser (dropping its tag-sized VLA and its
unchecked payload_length decrements).

Hangs: add bail-outs to every peripheral poll loop - RFM69 mode/TX/RX
waits, the EEPROM WIP poll, all six I2C TWINT spins, and the ADC. The
LDO is cut before sleeping, so a slow peripheral hung the firmware with
no watchdog armed.

Correctness: boot no longer wipes the EEPROM spool; the replayed packet
is sent once and deleted only on success; short ATOMIC_BLOCK sections
replace the blanket cli() that lost reed pulses during the radio window;
the I2C rail comes up before the RTC is touched; sleep_bod_disable() moves
into the timed sequence with the sleep race closed; sei() no longer runs
inside ISRs; REG_FDEV_MSB was 0x06 twice so deviation was 0; ADC uses
return ADC and a /64 prescaler; SS1 is an output before SPE is set.

VAL_DATA_MODUL_OOK was misnamed rather than wrong - 0x01 lands in
ModulationShaping, not ModulationType - so the register value is
unchanged and on-air behavior still matches the base station.

Verified: builds clean under -Wall -Wextra on both gnu17 and c23.
Not yet run on hardware.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YVJKatfeMJjAmuH9KYiLuv
This commit is contained in:
Ishan S. Patel
2026-08-31 22:54:56 -04:00
parent c87308caca
commit ed476473b6
26 changed files with 536 additions and 335 deletions
Download Patch File Download Diff File Expand all files Collapse all files
avr_code/rfm69.c
+71 -75
View File
@@ -1,8 +1,5 @@
#include "rfm69.h"
int8_t rssi;
uint8_t i;
uint8_t len_payload;
uint32_t msg_hash;
uint8_t p_hash_1;
uint8_t p_hash_2;
@@ -15,8 +12,6 @@ uint8_t c_hash_3;
bool cond_1;
bool cond_2;
bool cond_3;
bool cond_4;
bool cond_5;
DATA_SEND_STATUS send_message(tx_rx_data_struct tx_data)
{
@@ -46,19 +41,19 @@ DATA_SEND_STATUS send_message(tx_rx_data_struct tx_data)
cond_3 = cond_1 && cond_2;
if (cond_3 && (RX_DATA.flags == MSG_RECV_COUNTS_SUCCESS) && (RX_DATA.msg[3] == 0xFF)) {
#if DO_UART
uart_sendString(" RX DATA SUCCESS\n");
#if DO_UART
uart_sendString(" RX DATA SUCCESS\n");
#endif
return DATA_SEND_SUCCESS;
break;
} else if (
}
#if DO_UART
else if (
cond_3 && (RX_DATA.flags == MSG_RECV_COUNTS_FAIL) && (RX_DATA.msg[3] == 0x00)) {
uart_sendString(" RX DATA FAILED\n");
uart_sendString(" RX DATA FAILED\n");
} else {
uart_sendString(" RX DATA ANOTHER ERROR\n");
}
} else {
#endif
}
}
return DATA_NOT_SENT;
@@ -88,8 +83,11 @@ void uart_print_tx_rx_data(tx_rx_data_struct tx_rx_print)
void rfm69_write_msg(tx_rx_data_struct txrxd)
{
set_rfm69_rx_mode();
set_rfm69_tx_mode();
// TxStart is configured as FifoNotEmpty, so the radio begins transmitting
// the moment the first byte lands. Fill the FIFO from standby and only then
// switch to TX, otherwise the packet goes out ahead of its own payload.
set_rfm69_standby();
spi_rfm69_select(true);
spi_write(REG_FIFO | RFM69_SPI_WRITE);
if (txrxd.len > (60)) {
@@ -106,22 +104,30 @@ void rfm69_write_msg(tx_rx_data_struct txrxd)
}
spi_rfm69_select(false);
set_rfm69_tx_mode();
wait_tx_sent();
set_rfm69_rx_mode();
}
tx_rx_data_struct rfm69_read_msg()
tx_rx_data_struct rfm69_read_msg(void)
{
memset(RX_DATA.msg, ' ', sizeof(RX_DATA.msg));
spi_rfm69_select(true);
spi_write(REG_FIFO);
RX_DATA.len = spi_read() - 4;
uint8_t raw_len = spi_read();
RX_DATA.to = spi_read();
RX_DATA.from = spi_read();
RX_DATA.dtype = spi_read();
RX_DATA.flags = spi_read();
uint8_t len_f = RX_DATA.len;
// The length byte comes off the air and is not trustworthy: below 4 it
// underflows to ~252, above 60 it walks off the end of msg[].
uint8_t len_f = (raw_len < 4) ? 0 : (uint8_t)(raw_len - 4);
if (len_f > sizeof(RX_DATA.msg)) {
len_f = sizeof(RX_DATA.msg);
}
RX_DATA.len = len_f;
for (uint8_t idx_f = 0; idx_f < len_f; idx_f++) {
RX_DATA.msg[idx_f] = spi_read();
@@ -132,21 +138,11 @@ tx_rx_data_struct rfm69_read_msg()
return RX_DATA;
}
void rfm69_set_state(bool state)
{
SET_PIN_OUT(DDRC, DDC2);
if (!state) {
SET_PIN_HIGH(PORTC, PC2);
} else {
SET_PIN_LOW(PORTC, PC2);
}
}
uint8_t spi_read_rfm69_rt(uint8_t reg)
{
spi_rfm69_select(true);
spi_write(reg);
uint8_t data_read = spi_read(0xFF);
uint8_t data_read = spi_read();
spi_rfm69_select(false);
return data_read;
}
@@ -221,23 +217,25 @@ uint32_t hash_3bytes(unsigned const char* str, uint8_t str_len)
{
uint32_t hash = 0;
for (i = 0; i < str_len; i++) {
for (uint8_t i = 0; i < str_len; i++) {
hash = (hash * 31 + str[i]) % 0xFFFFFF;
}
return hash;
}
void set_rfm69_power_amp_boost()
void set_rfm69_power_amp_boost(void)
{
spi_write_rfm69_rt(REG_OCP, VAL_OCP_OFF);
spi_write_rfm69_rt(REG_TEST_PA1, VAL_TEST_PA1_BOOST);
spi_write_rfm69_rt(REG_TEST_PA2, VAL_TEST_PA2_BOOST);
}
void set_rfm69_power_amp_normal()
void set_rfm69_power_amp_normal(void)
{
spi_write_rfm69_rt(REG_TEST_PA1, VAL_TEST_PA1_NORMAL);
spi_write_rfm69_rt(REG_TEST_PA2, VAL_TEST_PA2_NORMAL);
};
spi_write_rfm69_rt(REG_OCP, VAL_OCP_ON);
}
void reset_txrx_struct(tx_rx_data_struct* s)
{
@@ -258,10 +256,15 @@ void set_rfm69_mode(uint8_t target_mode)
spi_write_rfm69_rt(REG_OP_MODE, mode);
}
void wait_tx_sent()
bool wait_tx_sent(void)
{
while (TX_NOT_SENT)
;
for (uint16_t attempts = 0; attempts < RFM69_TIMEOUT_MS; attempts++) {
if (TX_SENT) {
return true;
}
_delay_ms(1);
}
return false;
}
uint8_t hash(const char* str, uint8_t min, uint8_t max)
@@ -279,68 +282,69 @@ uint8_t hash(const char* str, uint8_t min, uint8_t max)
bool wait_rx_payload_ready_timeout(uint16_t attempts)
{
set_rfm69_rx_mode();
uint16_t counter = 0;
while (1) {
_delay_ms(1);
WHILE_BREAK(counter, attempts);
// Test the flag before spending the tick, so a payload that arrives on the
// last attempt is not thrown away.
for (uint16_t counter = 0; counter < attempts; counter++) {
if (RX_PAYLOAD_READY) {
return true;
break;
}
_delay_ms(1);
}
return RX_PAYLOAD_READY != 0;
}
bool wait_rx_payload_ready(void)
{
return wait_rx_payload_ready_timeout(RFM69_TIMEOUT_MS);
}
bool wait_rfm69_mode_ready(void)
{
for (uint16_t attempts = 0; attempts < RFM69_TIMEOUT_MS; attempts++) {
if (MODE_READY) {
return true;
}
_delay_ms(1);
}
return false;
;
}
void wait_rx_payload_ready()
{
while (RX_PAYLOAD_NOT_READY) { };
}
void wait_rfm69_mode_ready()
{
while (MODE_NOT_READY)
;
}
void set_rfm69_tx_mode()
void set_rfm69_tx_mode(void)
{
set_rfm69_power_amp_boost();
set_rfm69_mode(VAL_OPMODE_TX);
wait_rfm69_mode_ready();
};
}
void set_rfm69_rx_mode()
void set_rfm69_rx_mode(void)
{
set_rfm69_power_amp_normal();
set_rfm69_mode(VAL_OPMODE_RX);
wait_rfm69_mode_ready();
};
}
void set_rfm69_standby()
void set_rfm69_standby(void)
{
set_rfm69_power_amp_normal();
set_rfm69_mode(VAL_OPMODE_STDBY);
wait_rfm69_mode_ready();
}
void set_rfm69_sleep()
void set_rfm69_sleep(void)
{
set_rfm69_power_amp_normal();
set_rfm69_mode(VAL_OPMODE_SLEEP);
wait_rfm69_mode_ready();
}
void set_rfm69_idle()
void set_rfm69_idle(void)
{
set_rfm69_power_amp_normal();
set_rfm69_mode(VAL_OPMODE_STDBY);
wait_rfm69_mode_ready();
}
void reset_rfm69()
void reset_rfm69(void)
{
rfm69_reset_state(true);
_delay_ms(10);
@@ -348,14 +352,7 @@ void reset_rfm69()
_delay_ms(10);
}
void set_rfm69_tx_power()
{
uint8_t PA_LEVEL_SET
= VAL_PALEVEL_PA1_ON | VAL_PALEVEL_PA2_ON | ((20 + 14) & VAL_PALEVEL_PA1_OUTPUTPOWER);
spi_write_rfm69_rt(REG_PA_LEVEL, PA_LEVEL_SET);
}
void rfm69_init()
void rfm69_init(void)
{
reset_rfm69();
_delay_ms(100);
@@ -364,8 +361,6 @@ void rfm69_init()
spi_write_rfm69_rt(REG_FREQ_MIDDLE_SB, VAL_FREQ_433MHz_MID_SB);
spi_write_rfm69_rt(REG_FREQ_LSB, VAL_FREQ_433MHz_LSB);
spi_write_rfm69_rt(REG_FREQ_DEV_MSB, VAL_FREQ_DEV_MSB);
spi_write_rfm69_rt(
REG_FIFO_THRESH,
VAL_TX_START_FIFO_NOT_EMPTY | VAL_FIFO_LEVEL_INTERRUPT); // TX condition
@@ -377,14 +372,15 @@ void rfm69_init()
spi_write_rfm69_rt(REG_SYNC_CONFIG, VAL_SYNCWORDS_ON | VAL_SYNCWORDS_SIZE_2_BYTES);
spi_write_rfm69_rt(REG_DATA_MODUL,
VAL_DATA_PACKET_MODE | VAL_DATA_MODUL_OOK); // RegDataModul
VAL_DATA_PACKET_MODE | VAL_DATA_MODUL_FSK
| VAL_MODUL_SHAPING_GAUSS_BT_1_0); // RegDataModul
spi_write_rfm69_rt(REG_BITRATE_MSB,
VAL_BITRATE_250kbps_MSB); // RegBitrateMSB
spi_write_rfm69_rt(REG_BITRATE_LSB,
VAL_BITRATE_250kbps_LSB); // RegbBitrateLSB
spi_write_rfm69_rt(REG_FDEV_MSB, 0x10); // RegFdevMSB
spi_write_rfm69_rt(REG_FDEV_LSB, 0x00); // RegFdevLSB
spi_write_rfm69_rt(REG_FDEV_MSB, VAL_FDEV_MSB); // RegFdevMSB (0x05)
spi_write_rfm69_rt(REG_FDEV_LSB, VAL_FDEV_LSB); // RegFdevLSB (0x06)
spi_write_rfm69_rt(REG_RX_BW, 0xE0); // RegRxBw
spi_write_rfm69_rt(REG_AFC_BW, 0xE0); // RegAfcBw