Fix wake-from-sleep, RAM overrun, and peripheral hangs in AVR firmware

Three defects prevented the board from working at all:

- INT0/INT1 were falling-edge triggered. Edge detection needs the I/O
  clock, which SLEEP_MODE_PWR_DOWN stops, so neither the reed switch nor
  the RTC alarm could wake the MCU. Both are now low-level triggered (the
  only asynchronous mode), and each handler masks its own interrupt while
  the source is still asserted so the low level cannot retrigger. The reed
  and RTC pins also get their pull-ups; they were explicitly driven low.

- Statics were 1440 B of 2048 with a 538 B main frame, so the first NFC
  read ran the stack into .data. Shrank the oversized buffers and made the
  NFC scratch buffer static: statics 1440 -> 1038 B, main frame -> 204 B.

- The FIFO was filled after entering TX mode with TxStart = FifoNotEmpty,
  so transmission began before the payload was loaded. Load in standby.

Memory safety: clamp the unvalidated RX length (len - 4 underflowed to
>=252 into a 60-byte buffer), fix writes one byte past DATA_BUFFER_65,
fix the diameter copy length in st25dv.c, NUL-terminate remove_spaces,
and bounds-check the NDEF parser (dropping its tag-sized VLA and its
unchecked payload_length decrements).

Hangs: add bail-outs to every peripheral poll loop - RFM69 mode/TX/RX
waits, the EEPROM WIP poll, all six I2C TWINT spins, and the ADC. The
LDO is cut before sleeping, so a slow peripheral hung the firmware with
no watchdog armed.

Correctness: boot no longer wipes the EEPROM spool; the replayed packet
is sent once and deleted only on success; short ATOMIC_BLOCK sections
replace the blanket cli() that lost reed pulses during the radio window;
the I2C rail comes up before the RTC is touched; sleep_bod_disable() moves
into the timed sequence with the sleep race closed; sei() no longer runs
inside ISRs; REG_FDEV_MSB was 0x06 twice so deviation was 0; ADC uses
return ADC and a /64 prescaler; SS1 is an output before SPE is set.

VAL_DATA_MODUL_OOK was misnamed rather than wrong - 0x01 lands in
ModulationShaping, not ModulationType - so the register value is
unchanged and on-air behavior still matches the base station.

Verified: builds clean under -Wall -Wextra on both gnu17 and c23.
Not yet run on hardware.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YVJKatfeMJjAmuH9KYiLuv

avr_code/adc.c

@@ -1,6 +1,15 @@
 #include "adc.h"
 
-int8_t adc_Initialize()
+#define ADC_CONVERSION_TIMEOUT 1000U
+
+// The ADC needs a 50-200 kHz clock. At F_CPU = 8 MHz that is a /64 prescaler
+// (125 kHz); the old /2 ran it at 4 MHz, far out of spec.
+#define ADC_PRESCALER_64 ((1 << ADPS2) | (1 << ADPS1))
+
+// The 1.1 V bandgap reference needs time to settle after the mux is switched.
+#define ADC_SETTLE_US 200
+
+int8_t adc_Initialize(void)
 {
     //REFS VAL_0x01; ADLAR disabled; MUX adc0; 
     ADMUX = 0x40;
@@ -8,18 +17,17 @@ int8_t adc_Initialize()
     //ACME disabled; ADTS VAL_0x00; 
     ADCSRB = 0x00;
 
-    //ADEN enabled; ADSC disabled; ADATE disabled; ADIF disabled; ADIE disabled; ADPS VAL_0x01; 
-    ADCSRA = 0x81;
+    ADCSRA = (1 << ADEN) | ADC_PRESCALER_64;
 
     return 0;
 }
 
-void adc_Disable()
+void adc_Disable(void)
 {
 	ADCSRA &= ~(1 << ADEN);
 }
 
-void adc_Enable()
+void adc_Enable(void)
 {
 	ADCSRA |= (1 << ADEN);
 }
@@ -42,25 +50,37 @@ void adc_StartConversion(uint8_t channel)
 	ADMUX &= ~0x0f;
 	ADMUX |= channel;
     }
+	_delay_us(ADC_SETTLE_US);
 	ADCSRA |= (1 << ADSC);
 }
 
-bool adc_IsConversionDone()
+bool adc_IsConversionDone(void)
 {
 	return ((ADCSRA & (1 << ADIF)));
 }
 
 uint16_t adc_GetConversionResult(void)
 {
-	return (ADCL | ADCH << 8);
+	// ADC reads ADCL then ADCH in the right order. Reading the two volatile
+	// registers in one expression leaves the order unspecified, and taking ADCH
+	// first breaks the data-register lock and corrupts the result.
+	return ADC;
 }
 
 uint16_t adc_GetConversion(uint8_t channel)
 {
-
-
 	adc_StartConversion(channel);
-	while (!adc_IsConversionDone());
+
+	// A conversion is 13 ADC clocks (~104 us at 125 kHz); bail out rather than
+	// hang if the ADC is disabled or its clock is gated off.
+	uint16_t attempts = 0;
+	while (!adc_IsConversionDone()) {
+		if (++attempts > ADC_CONVERSION_TIMEOUT) {
+			return 0;
+		}
+		_delay_us(10);
+	}
+
 	uint16_t res = adc_GetConversionResult();
 	ADCSRA |= (1 << ADIF);
 	return res;