Refactor firmware for clarity; no functional changes
- main.c: file-header comment describing the hardware and operation, logic split into named phases (sleep_until_interrupt, wake_peripheral_rails, take_counts_snapshot, send_wheel_counts_report, handle_minute_alarm, init_all_hardware); shared state renamed to say what it is and made static. - rfm69.c: reorganized into six labeled sections; cond_1/2/3 and hash scratch globals replaced by a reply_acknowledges() helper with clear locals; packet layout and every init register write documented. - LOG() macro (compiled out when DO_UART is off) replaces the #if DO_UART blocks that obscured the logic. - Drivers: file-header comments; named RTC_REG_*/RTC_ALM_MASK_BIT constants; EEPROM spool scheme documented; ADC_CHANNEL_BANDGAP named; repeated pin if/else helpers collapsed to SET_PIN_TO(). - Removed unused globals/buffers and commented-out code; ran clang-format with the project style. Register writes and radio protocol are byte-identical. Builds clean under -Wall -Wextra on gnu17 and c23; flash 13028 -> 12830 B, static RAM 1038 -> 999 B. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01YVJKatfeMJjAmuH9KYiLuv
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@@ -1,61 +1,52 @@
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// GPIO helpers: every board control line lives here (except the two chip
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// selects, which stay with their SPI drivers). Each helper sets the pin's
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// direction on every call so it works no matter what ran before it.
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#include "states.h"
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void init_spi(void) {
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SET_PIN_OUT(DDRC, DDC1); // SCK1
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SET_PIN_OUT(DDRE, DDE3); // MOSI1
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SET_PIN_IN(DDRC, DDC0); // MISO1 (driven by the slave; no pull-up)
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void init_spi(void)
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{
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SET_PIN_OUT(DDRC, DDC1); // SCK1
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SET_PIN_OUT(DDRE, DDE3); // MOSI1
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SET_PIN_IN(DDRC, DDC0); // MISO1 (driven by the slave; no pull-up)
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// SS1 must be an output before SPE is set. If it is left as an input and
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// reads low, the hardware clears MSTR and the port silently stops being
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// a master.
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SET_PIN_OUT(DDRE, DDE2);
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SET_PIN_HIGH(PORTE, PE2);
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// SS1 must be an output before SPE is set. If it is left as an input and
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// reads low, the hardware clears MSTR and the port silently stops being a
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// master.
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SET_PIN_OUT(DDRE, DDE2);
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SET_PIN_HIGH(PORTE, PE2);
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SPCR1 = (1 << SPE1) | (1 << MSTR1); // Enable, Master, SPR1:0 = 00 -> f_osc/4
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}
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void rfm69_reset_state(bool state) {
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SET_PIN_OUT(DDRC, DDC2);
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if (state) {
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SET_PIN_HIGH(PORTC, PC2);
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} else {
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SET_PIN_LOW(PORTC, PC2);
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}
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}
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SPCR1 = (1 << SPE1) | (1 << MSTR1); // Enable, Master, SPR1:0 = 00 -> f_osc/4
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}
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void led_1_set_state(bool state) {
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SET_PIN_OUT(DDRD, DDD4);
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if (state) {
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SET_PIN_HIGH(PORTD, PD4);
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} else {
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SET_PIN_LOW(PORTD, PD4);
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}
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}
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// RFM69 reset line: high holds the radio in reset
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void rfm69_reset_state(bool state)
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{
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SET_PIN_OUT(DDRC, DDC2);
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SET_PIN_TO(PORTC, PC2, state);
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}
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void led_2_set_state(bool state) {
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SET_PIN_OUT(DDRD, DDD6);
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if (state) {
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SET_PIN_HIGH(PORTD, PD6);
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} else {
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SET_PIN_LOW(PORTD, PD6);
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}
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}
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void led_1_set_state(bool state)
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{
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SET_PIN_OUT(DDRD, DDD4);
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SET_PIN_TO(PORTD, PD4, state);
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}
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void led_3_set_state(bool state) {
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SET_PIN_OUT(DDRD, DDD7);
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if (state) {
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SET_PIN_HIGH(PORTD, PD7);
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} else {
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SET_PIN_LOW(PORTD, PD7);
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}
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}
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void led_2_set_state(bool state)
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{
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SET_PIN_OUT(DDRD, DDD6);
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SET_PIN_TO(PORTD, PD6, state);
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}
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void ldo_set_state(bool state) {
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SET_PIN_OUT(DDRC, DDC3);
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if (state) {
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SET_PIN_HIGH(PORTC, PC3);
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} else {
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SET_PIN_LOW(PORTC, PC3);
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}
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}
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void led_3_set_state(bool state)
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{
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SET_PIN_OUT(DDRD, DDD7);
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SET_PIN_TO(PORTD, PD7, state);
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}
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// Enable line of the LDO that powers the radio and EEPROM
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void ldo_set_state(bool state)
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{
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SET_PIN_OUT(DDRC, DDC3);
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SET_PIN_TO(PORTC, PC3, state);
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}
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