thebears
ed476473b6
Three defects prevented the board from working at all: - INT0/INT1 were falling-edge triggered. Edge detection needs the I/O clock, which SLEEP_MODE_PWR_DOWN stops, so neither the reed switch nor the RTC alarm could wake the MCU. Both are now low-level triggered (the only asynchronous mode), and each handler masks its own interrupt while the source is still asserted so the low level cannot retrigger. The reed and RTC pins also get their pull-ups; they were explicitly driven low. - Statics were 1440 B of 2048 with a 538 B main frame, so the first NFC read ran the stack into .data. Shrank the oversized buffers and made the NFC scratch buffer static: statics 1440 -> 1038 B, main frame -> 204 B. - The FIFO was filled after entering TX mode with TxStart = FifoNotEmpty, so transmission began before the payload was loaded. Load in standby. Memory safety: clamp the unvalidated RX length (len - 4 underflowed to >=252 into a 60-byte buffer), fix writes one byte past DATA_BUFFER_65, fix the diameter copy length in st25dv.c, NUL-terminate remove_spaces, and bounds-check the NDEF parser (dropping its tag-sized VLA and its unchecked payload_length decrements). Hangs: add bail-outs to every peripheral poll loop - RFM69 mode/TX/RX waits, the EEPROM WIP poll, all six I2C TWINT spins, and the ADC. The LDO is cut before sleeping, so a slow peripheral hung the firmware with no watchdog armed. Correctness: boot no longer wipes the EEPROM spool; the replayed packet is sent once and deleted only on success; short ATOMIC_BLOCK sections replace the blanket cli() that lost reed pulses during the radio window; the I2C rail comes up before the RTC is touched; sleep_bod_disable() moves into the timed sequence with the sleep race closed; sei() no longer runs inside ISRs; REG_FDEV_MSB was 0x06 twice so deviation was 0; ADC uses return ADC and a /64 prescaler; SS1 is an output before SPE is set. VAL_DATA_MODUL_OOK was misnamed rather than wrong - 0x01 lands in ModulationShaping, not ModulationType - so the register value is unchanged and on-air behavior still matches the base station. Verified: builds clean under -Wall -Wextra on both gnu17 and c23. Not yet run on hardware. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01YVJKatfeMJjAmuH9KYiLuv
71 lines
2.0 KiB
C
71 lines
2.0 KiB
C
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#include "interrupts.h"
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void init_pins(void) {
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// The reed switch (PD3/INT1) switches to ground and the RTC alarm output
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// (PD2/INT0) is open-drain, so both need the internal pull-up. Leaving them
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// floating makes the inputs self-trigger.
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SET_PIN_IN(DDRD, DDD3);
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SET_PIN_HIGH(PORTD, PD3);
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SET_PIN_IN(DDRD, DDD2);
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SET_PIN_HIGH(PORTD, PD2);
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}
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// Both external interrupts are configured low-level triggered (ISCn1:0 = 00).
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// Edge detection needs the I/O clock, which SLEEP_MODE_PWR_DOWN stops, so a
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// falling-edge INT0/INT1 can never wake the MCU. Only level detection is
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// asynchronous. Each handler masks its own interrupt while the source is still
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// asserted, so the low level does not retrigger in a loop.
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void set_up_reed_interrupt(void) {
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EICRA &= ~((1 << ISC11) | (1 << ISC10));
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EIMSK |= (1 << INT1);
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}
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void set_up_minute_interrupt(void) {
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EICRA &= ~((1 << ISC01) | (1 << ISC00));
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EIMSK |= (1 << INT0);
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}
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void reed_interrupt_enable(void) {
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EIFR = (1 << INTF1); // Drop anything latched while we were masked
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EIMSK |= (1 << INT1);
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}
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void minute_interrupt_enable(void) {
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EIFR = (1 << INTF0);
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EIMSK |= (1 << INT0);
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}
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void wdt_isr_enable(void) {
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uint8_t sreg = SREG;
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cli();
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wdt_reset();
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// WDRF keeps WDE set, which would block the write below, so it must go
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// first. The unlock is a single assignment: a read-modify-write does not
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// open the 4-cycle change window.
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MCUSR &= ~(1 << WDRF);
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WDTCSR = (1 << WDCE) | (1 << WDE);
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// WDP[3:0] = 0b011 -> 0.125 s. Interrupt mode only (WDE clear), so an
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// expiry wakes us to clear the debounce instead of resetting the part.
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WDTCSR = (1 << WDIE) | (1 << WDP1) | (1 << WDP0);
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SREG = sreg; // Restore, never blanket-sei(): these run inside an ISR
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}
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void wdt_isr_disable(void) {
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uint8_t sreg = SREG;
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cli();
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wdt_reset();
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MCUSR &= ~(1 << WDRF);
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WDTCSR = (1 << WDCE) | (1 << WDE);
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WDTCSR = 0x00;
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SREG = sreg;
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}
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