thebears
ed476473b6
Three defects prevented the board from working at all: - INT0/INT1 were falling-edge triggered. Edge detection needs the I/O clock, which SLEEP_MODE_PWR_DOWN stops, so neither the reed switch nor the RTC alarm could wake the MCU. Both are now low-level triggered (the only asynchronous mode), and each handler masks its own interrupt while the source is still asserted so the low level cannot retrigger. The reed and RTC pins also get their pull-ups; they were explicitly driven low. - Statics were 1440 B of 2048 with a 538 B main frame, so the first NFC read ran the stack into .data. Shrank the oversized buffers and made the NFC scratch buffer static: statics 1440 -> 1038 B, main frame -> 204 B. - The FIFO was filled after entering TX mode with TxStart = FifoNotEmpty, so transmission began before the payload was loaded. Load in standby. Memory safety: clamp the unvalidated RX length (len - 4 underflowed to >=252 into a 60-byte buffer), fix writes one byte past DATA_BUFFER_65, fix the diameter copy length in st25dv.c, NUL-terminate remove_spaces, and bounds-check the NDEF parser (dropping its tag-sized VLA and its unchecked payload_length decrements). Hangs: add bail-outs to every peripheral poll loop - RFM69 mode/TX/RX waits, the EEPROM WIP poll, all six I2C TWINT spins, and the ADC. The LDO is cut before sleeping, so a slow peripheral hung the firmware with no watchdog armed. Correctness: boot no longer wipes the EEPROM spool; the replayed packet is sent once and deleted only on success; short ATOMIC_BLOCK sections replace the blanket cli() that lost reed pulses during the radio window; the I2C rail comes up before the RTC is touched; sleep_bod_disable() moves into the timed sequence with the sleep race closed; sei() no longer runs inside ISRs; REG_FDEV_MSB was 0x06 twice so deviation was 0; ADC uses return ADC and a /64 prescaler; SS1 is an output before SPE is set. VAL_DATA_MODUL_OOK was misnamed rather than wrong - 0x01 lands in ModulationShaping, not ModulationType - so the register value is unchanged and on-air behavior still matches the base station. Verified: builds clean under -Wall -Wextra on both gnu17 and c23. Not yet run on hardware. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01YVJKatfeMJjAmuH9KYiLuv
57 lines
2.2 KiB
C
57 lines
2.2 KiB
C
#include "defines.h"
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#include "uart.h"
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#include <avr/io.h>
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#ifndef i2c_H
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#define i2c_H
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#define TWSR TWSR0
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#define TWDR TWDR0
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#define TWBR TWBR0
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#define TWCR TWCR0
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#define I2C_START_WRITE(device_addr) \
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{ \
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if (i2c_start((device_addr << 1) | 0x00)) { \
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return 1; \
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} \
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}
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#define I2C_START_READ(device_addr) \
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{ \
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if (i2c_start((device_addr << 1) | 0x01)) { \
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return 1; \
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} \
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}
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// A byte at F_SCL takes well under 100 us; anything past this means the bus is
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// stuck (peripheral unpowered, SDA held low) and we must not spin forever.
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#define I2C_TIMEOUT_LOOPS 20000U
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void i2c_init(void);
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uint8_t i2c_start(uint8_t address);
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uint8_t write_one_byte(uint8_t device_addr, uint8_t register_addr,
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uint8_t data);
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uint8_t write_n_bytes(uint8_t device_addr, uint8_t register_addr, uint8_t *data,
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uint8_t n_bytes);
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uint8_t read_one_byte_16bit_addr_no_err_register(uint8_t device_addr, uint16_t register_addr);
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uint8_t read_one_byte_16bit_addr(uint8_t device_addr, uint16_t register_addr,
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uint8_t *data);
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uint8_t read_n_bytes_16bit_addr(uint8_t device_addr, uint16_t register_addr, uint8_t *data,
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uint8_t n_bytes);
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uint8_t read_one_byte_no_err_register(uint8_t device_addr, uint8_t register_addr);
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uint8_t read_one_byte(uint8_t device_addr, uint8_t register_addr,
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uint8_t *data);
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uint8_t read_n_bytes(uint8_t device_addr, uint8_t register_addr, uint8_t *data,
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uint8_t n_bytes);
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void i2c_stop(void);
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uint8_t i2c_read_ack(void);
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uint8_t i2c_read_nack(void);
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uint8_t i2c_write(uint8_t data);
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#endif |