thebears
ed476473b6
Three defects prevented the board from working at all: - INT0/INT1 were falling-edge triggered. Edge detection needs the I/O clock, which SLEEP_MODE_PWR_DOWN stops, so neither the reed switch nor the RTC alarm could wake the MCU. Both are now low-level triggered (the only asynchronous mode), and each handler masks its own interrupt while the source is still asserted so the low level cannot retrigger. The reed and RTC pins also get their pull-ups; they were explicitly driven low. - Statics were 1440 B of 2048 with a 538 B main frame, so the first NFC read ran the stack into .data. Shrank the oversized buffers and made the NFC scratch buffer static: statics 1440 -> 1038 B, main frame -> 204 B. - The FIFO was filled after entering TX mode with TxStart = FifoNotEmpty, so transmission began before the payload was loaded. Load in standby. Memory safety: clamp the unvalidated RX length (len - 4 underflowed to >=252 into a 60-byte buffer), fix writes one byte past DATA_BUFFER_65, fix the diameter copy length in st25dv.c, NUL-terminate remove_spaces, and bounds-check the NDEF parser (dropping its tag-sized VLA and its unchecked payload_length decrements). Hangs: add bail-outs to every peripheral poll loop - RFM69 mode/TX/RX waits, the EEPROM WIP poll, all six I2C TWINT spins, and the ADC. The LDO is cut before sleeping, so a slow peripheral hung the firmware with no watchdog armed. Correctness: boot no longer wipes the EEPROM spool; the replayed packet is sent once and deleted only on success; short ATOMIC_BLOCK sections replace the blanket cli() that lost reed pulses during the radio window; the I2C rail comes up before the RTC is touched; sleep_bod_disable() moves into the timed sequence with the sleep race closed; sei() no longer runs inside ISRs; REG_FDEV_MSB was 0x06 twice so deviation was 0; ADC uses return ADC and a /64 prescaler; SS1 is an output before SPE is set. VAL_DATA_MODUL_OOK was misnamed rather than wrong - 0x01 lands in ModulationShaping, not ModulationType - so the register value is unchanged and on-air behavior still matches the base station. Verified: builds clean under -Wall -Wextra on both gnu17 and c23. Not yet run on hardware. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01YVJKatfeMJjAmuH9KYiLuv
154 lines
4.5 KiB
C
154 lines
4.5 KiB
C
/*
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* File: rfm69.h
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* Author: thebears
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*
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* Created on December 11, 2024, 2:05 PM
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*/
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#include "defines.h"
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#include "spi.h"
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#include "states.h"
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#include "uart.h"
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#include <avr/io.h>
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#include <stdbool.h>
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#include <string.h>
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#include <util/delay.h>
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#ifndef RFM69_H
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#define RFM69_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define MODE_READY (spi_read_rfm69_rt(REG_IRQ_FLAGS1) & VAL_IRQ_FLAGS1_MODEREADY)
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#define MODE_NOT_READY (!MODE_READY)
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#define RX_PAYLOAD_READY (spi_read_rfm69_rt(REG_IRQ_FLAGS2) & VAL_IRQ_FLAGS2_RX_PAYLOADREADY)
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#define RX_PAYLOAD_NOT_READY (!RX_PAYLOAD_READY)
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#define TX_SENT (spi_read_rfm69_rt(REG_IRQ_FLAGS2) & VAL_IRQ_FLAGS2_TX_SENT)
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#define TX_NOT_SENT (!TX_SENT)
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// Bail-out for every RFM69 poll loop: an absent or unpowered radio must not
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// hang the firmware, since no watchdog reset is armed.
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#define RFM69_TIMEOUT_MS 100U
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#define REG_FIFO 0x00
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#define REG_FREQ_MSB 0x07
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#define REG_FREQ_MIDDLE_SB 0x08
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#define REG_FREQ_LSB 0x09
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#define REG_FIFO_THRESH 0x3c
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#define REG_TEST_DAGC 0x6f
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#define REG_SYNC_CONFIG 0x2e
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#define REG_SYNC_VALUE_1 0x2f
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#define REG_OP_MODE 0x01
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#define REG_DATA_MODUL 0x02
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#define REG_BITRATE_MSB 0x03
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#define REG_BITRATE_LSB 0x04
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#define REG_FDEV_MSB 0x05
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#define REG_FDEV_LSB 0x06
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#define REG_RX_BW 0x19
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#define REG_AFC_BW 0x1A
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#define REG_PACKET_CONFIG_1 0x37
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#define REG_PREAMBLE_MSB 0x2C
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#define REG_PREAMBLE_LSB 0x2D
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#define REG_PA_LEVEL 0x11
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#define REG_TEST_PA1 0x5A
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#define REG_TEST_PA2 0x5C
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#define REG_IRQ_FLAGS1 0x27
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#define REG_IRQ_FLAGS2 0x28
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#define REG_RSSI_VALUE 0x24
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#define REG_OCP 0x13
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// Over-current protection must be off while the PA boost registers are set,
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// per the datasheet's high-power (+20 dBm) sequence.
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#define VAL_OCP_OFF 0x0F
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#define VAL_OCP_ON 0x1A
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#define VAL_FDEV_MSB 0x10
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#define VAL_FDEV_LSB 0x00
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#define VAL_TEST_DAGC_DEFAULT 0x30
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#define VAL_DATA_PACKET_MODE 0x00
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#define VAL_BITRATE_250kbps_MSB 0x00
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#define VAL_BITRATE_250kbps_LSB 0x80
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#define VAL_DATA_MODUL_FSK 0x00 // RegDataModul ModulationType is bits 4:3
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#define VAL_MODUL_SHAPING_GAUSS_BT_1_0 0x01
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#define VAL_TX_START_FIFO_NOT_EMPTY 0x80
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#define VAL_FIFO_LEVEL_INTERRUPT 0x0f
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#define VAL_IRQ_FLAGS1_MODEREADY 0x80
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#define VAL_IRQ_FLAGS2_TX_SENT 0x08
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#define VAL_IRQ_FLAGS2_RX_PAYLOADREADY 0x04
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#define VAL_OPMODE_MASK 0x1c
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#define VAL_OPMODE_SLEEP 0x00
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#define VAL_OPMODE_STDBY 0x04
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#define VAL_OPMODE_TX 0x0c
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#define VAL_OPMODE_RX 0x10
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#define VAL_SYNCWORDS_ON 0x80
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#define VAL_SYNCWORDS_SIZE_2_BYTES 0x08
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#define VAL_PACKET_VARIABLE_LENGTH 0x80
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#define VAL_PACKET_WHITENING 0x40
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#define VAL_PACKET_CRCON 0x10
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#define VAL_PA_PA1_ON 0x40
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#define VAL_PA_PA2_ON 0x20
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#define VAL_PA_20dB 0x1F
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#define VAL_PALEVEL_PA1_ON 0x40
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#define VAL_PALEVEL_PA2_ON 0x20
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#define VAL_PALEVEL_PA1_OUTPUTPOWER 0x1f
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#define VAL_TEST_PA1_NORMAL 0x55
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#define VAL_TEST_PA2_NORMAL 0x70
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#define VAL_TEST_PA1_BOOST 0x5d
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#define VAL_TEST_PA2_BOOST 0x7c
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#define RFM69_SPI_WRITE 0x80
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// Target frequency is 433 MHz.
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// Equation is 32MHz/2^19 = 61.03515625. 433 MHz/61.03515625 = 7,094,272
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// 7,094,272 = 01101100 01000000 00000000 = 0x6C 0x40 0x00
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// Target frequency is 434.0 MHz.
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// Equation is 32MHz/2^19 = 61.03515625. 434 MHz/61.03515625 = 7,110,656
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// 7,110,656 = 01101100 01000000 00000000 = 0x6C 0x80 0x00
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#define VAL_FREQ_433MHz_MSB 0x6c
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#define VAL_FREQ_433MHz_MID_SB 0x80
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#define VAL_FREQ_433MHz_LSB 0x00
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DATA_SEND_STATUS send_message(tx_rx_data_struct tx_data);
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uint8_t spi_read_rfm69_rt(uint8_t reg);
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uint8_t spi_write_rfm69_rt(uint8_t reg, uint8_t val);
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uint8_t spi_write_rfm69_multiple_rt(uint8_t reg, const char* vals, uint8_t len);
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void set_rfm69_power_amp_boost(void);
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void set_rfm69_power_amp_normal(void);
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tx_rx_data_struct rfm69_read_msg(void);
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void reset_txrx_struct(tx_rx_data_struct* s);
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void rfm69_write_msg(tx_rx_data_struct txrxd);
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void set_rfm69_mode(uint8_t mode);
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bool wait_rfm69_mode_ready(void);
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void set_rfm69_tx_mode(void);
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bool wait_tx_sent(void);
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bool wait_rx_payload_ready(void);
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void reset_rfm69(void);
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void set_rfm69_rx_mode(void);
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void set_rfm69_standby(void);
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void set_rfm69_sleep(void);
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void set_rfm69_idle(void);
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void rfm69_init(void);
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bool wait_rx_payload_ready_timeout(uint16_t attempts);
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uint8_t hash(const char* str, uint8_t min, uint8_t max);
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uint32_t hash_3bytes(unsigned const char* str, uint8_t str_len);
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void uart_print_tx_rx_data(tx_rx_data_struct tx_rx_print);
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tx_rx_data_struct generate_wheel_counts_message(
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identifier_results idd, time_struct time, uint16_t battery_value, volatile uint16_t counts[15]);
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#ifdef __cplusplus
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}
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#endif
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#endif /* RFM69_H */
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