📝 KHz => kHz (#23512)
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@@ -491,9 +491,9 @@
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* 1 : 4 - 5 MHz
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* 2 : 2 - 2.5 MHz
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* 3 : 1 - 1.25 MHz
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* 4 : 500 - 625 KHz
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* 5 : 250 - 312 KHz
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* 6 : 125 - 156 KHz
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* 4 : 500 - 625 kHz
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* 5 : 250 - 312 kHz
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* 6 : 125 - 156 kHz
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*/
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void spiInit(uint8_t spiRate) {
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switch (spiRate) {
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@@ -25,7 +25,7 @@
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* is NOT used to directly toggle pins. The ISR writes to the pin assigned to
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* that interrupt.
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*
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* All PWMs use the same repetition rate. The G2 needs about 10KHz min in order to
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* All PWMs use the same repetition rate. The G2 needs about 10kHz min in order to
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* not have obvious ripple on the Vref signals.
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*
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* The data structures are setup to minimize the computation done by the ISR which
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@@ -53,7 +53,7 @@
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* The net result is that both the g_pinStatus[pin] array and the PIO_OSR register
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* needs to be looked at when determining if a pin is an input or an output.
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*
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* b) Due has only pins 6, 7, 8 & 9 enabled for PWMs. FYI - they run at 1KHz
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* b) Due has only pins 6, 7, 8 & 9 enabled for PWMs. FYI - they run at 1kHz
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*
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* c) NUM_DIGITAL_PINS does not include the analog pins
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*
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@@ -62,7 +62,7 @@ const tTimerConfig timer_config[NUM_HARDWARE_TIMERS] = {
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Timer_clock1: Prescaler 2 -> 42MHz
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Timer_clock2: Prescaler 8 -> 10.5MHz
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Timer_clock3: Prescaler 32 -> 2.625MHz
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Timer_clock4: Prescaler 128 -> 656.25KHz
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Timer_clock4: Prescaler 128 -> 656.25kHz
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*/
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void HAL_timer_start(const uint8_t timer_num, const uint32_t frequency) {
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@@ -74,9 +74,9 @@ extern "C" {
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//@{
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enum genclk_source {
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GENCLK_PCK_SRC_SLCK_RC = 0, //!< Internal 32KHz RC oscillator as PCK source clock
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GENCLK_PCK_SRC_SLCK_XTAL = 1, //!< External 32KHz crystal oscillator as PCK source clock
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GENCLK_PCK_SRC_SLCK_BYPASS = 2, //!< External 32KHz bypass oscillator as PCK source clock
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GENCLK_PCK_SRC_SLCK_RC = 0, //!< Internal 32kHz RC oscillator as PCK source clock
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GENCLK_PCK_SRC_SLCK_XTAL = 1, //!< External 32kHz crystal oscillator as PCK source clock
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GENCLK_PCK_SRC_SLCK_BYPASS = 2, //!< External 32kHz bypass oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_4M_RC = 3, //!< Internal 4MHz RC oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_8M_RC = 4, //!< Internal 8MHz RC oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_12M_RC = 5, //!< Internal 12MHz RC oscillator as PCK source clock
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@@ -93,9 +93,9 @@ extern "C" {
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//! \name Oscillator identifiers
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//@{
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#define OSC_SLCK_32K_RC 0 //!< Internal 32KHz RC oscillator.
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#define OSC_SLCK_32K_XTAL 1 //!< External 32KHz crystal oscillator.
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#define OSC_SLCK_32K_BYPASS 2 //!< External 32KHz bypass oscillator.
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#define OSC_SLCK_32K_RC 0 //!< Internal 32kHz RC oscillator.
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#define OSC_SLCK_32K_XTAL 1 //!< External 32kHz crystal oscillator.
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#define OSC_SLCK_32K_BYPASS 2 //!< External 32kHz bypass oscillator.
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#define OSC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator.
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#define OSC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator.
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#define OSC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator.
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@@ -105,9 +105,9 @@ extern "C" {
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//! \name Oscillator clock speed in hertz
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//@{
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#define OSC_SLCK_32K_RC_HZ CHIP_FREQ_SLCK_RC //!< Internal 32KHz RC oscillator.
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#define OSC_SLCK_32K_XTAL_HZ BOARD_FREQ_SLCK_XTAL //!< External 32KHz crystal oscillator.
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#define OSC_SLCK_32K_BYPASS_HZ BOARD_FREQ_SLCK_BYPASS //!< External 32KHz bypass oscillator.
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#define OSC_SLCK_32K_RC_HZ CHIP_FREQ_SLCK_RC //!< Internal 32kHz RC oscillator.
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#define OSC_SLCK_32K_XTAL_HZ BOARD_FREQ_SLCK_XTAL //!< External 32kHz crystal oscillator.
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#define OSC_SLCK_32K_BYPASS_HZ BOARD_FREQ_SLCK_BYPASS //!< External 32kHz bypass oscillator.
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#define OSC_MAINCK_4M_RC_HZ CHIP_FREQ_MAINCK_RC_4MHZ //!< Internal 4MHz RC oscillator.
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#define OSC_MAINCK_8M_RC_HZ CHIP_FREQ_MAINCK_RC_8MHZ //!< Internal 8MHz RC oscillator.
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#define OSC_MAINCK_12M_RC_HZ CHIP_FREQ_MAINCK_RC_12MHZ //!< Internal 12MHz RC oscillator.
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@@ -156,9 +156,9 @@ extern "C" {
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//! \name Master Clock Sources (MCK)
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//@{
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#define SYSCLK_SRC_SLCK_RC 0 //!< Internal 32KHz RC oscillator as master source clock
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#define SYSCLK_SRC_SLCK_XTAL 1 //!< External 32KHz crystal oscillator as master source clock
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#define SYSCLK_SRC_SLCK_BYPASS 2 //!< External 32KHz bypass oscillator as master source clock
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#define SYSCLK_SRC_SLCK_RC 0 //!< Internal 32kHz RC oscillator as master source clock
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#define SYSCLK_SRC_SLCK_XTAL 1 //!< External 32kHz crystal oscillator as master source clock
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#define SYSCLK_SRC_SLCK_BYPASS 2 //!< External 32kHz bypass oscillator as master source clock
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#define SYSCLK_SRC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator as master source clock
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#define SYSCLK_SRC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator as master source clock
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#define SYSCLK_SRC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator as master source clock
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@@ -39,7 +39,7 @@ void watchdogSetup() {
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uint32_t timeout = TERN(WATCHDOG_DURATION_8S, 8000, 4000);
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// Calculate timeout value in WDT counter ticks: This assumes
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// the slow clock is running at 32.768 KHz watchdog
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// the slow clock is running at 32.768 kHz watchdog
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// frequency is therefore 32768 / 128 = 256 Hz
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timeout = (timeout << 8) / 1000;
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if (timeout == 0)
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