Changes to STM32F1 HAL (#8833)

Some to correct missing files from previous PR to completely avoid
HardwareTimer Class (reduce overhead). Some changes to formatting.
Changes to DMA ADC to work correctly.
Change to F1 sanity check.
This commit is contained in:
victorpv
2017-12-20 16:16:36 -06:00
committed by Scott Lahteine
parent 913d9e9a59
commit 2ec4113cb2
8 changed files with 129 additions and 99 deletions

View File

@@ -82,18 +82,35 @@ const tTimerConfig TimerConfig [NUM_HARDWARE_TIMERS] = {
// Public functions
// --------------------------------------------------------------------------
/*
Timer_clock1: Prescaler 2 -> 42MHz
Timer_clock2: Prescaler 8 -> 10.5MHz
Timer_clock3: Prescaler 32 -> 2.625MHz
Timer_clock4: Prescaler 128 -> 656.25kHz
*/
/**
* Timer_clock1: Prescaler 2 -> 36 MHz
* Timer_clock2: Prescaler 8 -> 9 MHz
* Timer_clock3: Prescaler 32 -> 2.25 MHz
* Timer_clock4: Prescaler 128 -> 562.5 kHz
*/
/**
* TODO: Calculate Timer prescale value, so we get the 32bit to adjust
*/
void HAL_timer_start(uint8_t timer_num, uint32_t frequency) {
nvic_irq_num irq_num;
switch (timer_num) {
case 1: irq_num = NVIC_TIMER1_CC; break;
case 2: irq_num = NVIC_TIMER2; break;
case 3: irq_num = NVIC_TIMER3; break;
case 4: irq_num = NVIC_TIMER4; break;
case 5: irq_num = NVIC_TIMER5; break;
default:
/**
* We should not get here, add Sanitycheck for timer number. Should be a general timer
* since basic timers do not have CC channels.
* Advanced timers should be skipped if possible too, and are not listed above.
*/
break;
}
nvic_irq_set_priority(irq_num, 0xF); // this is the lowest settable priority, but should still be over USB
switch (timer_num) {
case STEP_TIMER_NUM:
timer_pause(STEP_TIMER_DEV);