Apply SBI/CBI/TEST in HAL
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@@ -71,8 +71,8 @@ static void TXBegin() {
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volatile uint32_t ICER[32];
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};
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NVICMin * nvicBase = (NVICMin*)0xE000E100;
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nvicBase->ICER[nvicIndex / 32] |= _BV32(nvicIndex % 32);
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NVICMin *nvicBase = (NVICMin*)0xE000E100;
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SBI32(nvicBase->ICER[nvicIndex >> 5], nvicIndex & 0x1F);
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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